A Field Programmable Sequencer and Memory with Middle Grained Programmability Optimized for MCU Peripherals

A Field Programmable Sequencer and Memory (FPSM), which is a programmable unit exclusively optimized for peripherals on a micro controller unit, is proposed. The FPSM functions as not only the peripherals but also the standard built-in memory. The FPSM provides easier programmability with a smaller area overhead, especially when compared with the FPGA. The FPSM is implemented on the FPGA and the programmability and performance for basic peripherals such as the 8 bit counter and 8 bit accuracy Pulse Width Modulation are emulated on the FPGA. Furthermore, the FPSM core with a 4K bit SRAM is fabricated in 0.18µm 5 metal CMOS process technology. The FPSM is an half the area of FPGA, its power consumption is less than one-fifth.Embargo Period 6 month

An Embedded Programmable Logic Matrix (ePLX) for flexible functions on SoC

Abstract — In this paper, we propose embedded programmable logic matrix (ePLX) which is suitable for flexible System on Chip (SoC). The ePLX architecture is based on the dense two input Look-Up-Table(LUT) array and the hierarchical wiring resources, which are global/local wiring resources and with simple mapping tools. The compile flow of ePLX is also the simple one with the standard design environments, basically. We have verified the advantage of this architecture by programming the function module and mapping the circuits with high usage efficiency and doubling operation speed. The physical architecture of ePLX uses the divided power supply LUT and wiring resources that consists of SRAM with CMOS transfer gate switch elements. These techniques enable to handle the 0.6V level FV controllable programmable devices for the power management SoC. The ePLX can provide the unique additional merits for many applications under the platform design environments. I